An integrated gate shift register integrates a gate pulse output register on a panel so as to reduce the number of ICs and decrease the cost. Implementations for the integrated gate shift register are various and may comprise different numbers of transistors and capacitors, and its common structure is, for example, 12T1C, 9T1C, 13T1C, etc.
Generally, one shift register comprises a plurality of stages of shift register units, and each stage of shift register unit outputs a high potential signal only during a very short time and outputs a low potential signal, generally as a VSS signal, during other time.
As mentioned above, each stage of shift register unit outputs the high potential signal only during the very short time and outputs the low potential signal during other time which occupies above 99% commonly. Meanwhile, the VSS signal is always outputted by a pulling-down transistor, and when it is required that the shift register unit outputs a low potential signal, the pulling-down transistor is required being in a turn-on state by a high potential in order to pull down a potential with the VSS signal. Therefore, a gate of the pulling-down transistor is in a high potential state over a long period of time and has a very high duty ratio voltage, such that this manner would cause the pulling-down transistor to age rapidly, and alternatively a mobility of the pulling-down transistor decreases and its current decreases accordingly, which causes a fault in an entire circuit and affects a lifespan of a product.
The existing shift register unit would be described below in connection with FIG. 1.
FIG. 1 illustrates the existing shift register unit comprising nine thin film field effect transistors (briefly referred to as TFT thereafter) M01, M02, M03, M05, M06, M08, M13, M15, M17 and one capacitor C1. In FIG. 1, the pulling-down transistor is M03, and detailed connection relationship among respective components in the shift register unit and a principle of the shift register unit are as follows.
The TFT M02 outputs an OUTPUT to an outputting terminal according to a signal CLK inputted from a clock signal inputting terminal. A source of the TFT M02 receives the CLK signal, a drain thereof is connected with the OUTPUT terminal, and a gate thereof is connected with a pulling-up node PU; a gate and a source of the M01 are connected with an inputting terminal INPUT, and a drain thereof is connected with the pulling-up node PU; one terminal of the capacitor C1 is connected with the pulling-up node PU, and the other terminal is connected with the outputting node OUTPUT.
When the outputting terminal OUTPUT is inactive, the pulling-up node PU and the outputting node OUTPUT at a present stage are needed to be pulled down so as to keep them at a low potential. A circuit for pulling down the pulling-up node PU and the outputting node OUTPUT at the present stage comprises the TFTs M03 and M15, wherein the M15 is used to pull down a potential at the PU node while the M03 pulls down a potential at the OUTPUT node.
Gates of the TFTs M03 and M15 are connected with a PD node whose potential is controlled by the TFTs M05, M13 and M08, wherein the M05 and M13 pull down the potential at the PD node when the INPUT and PU node are at a high potential, respectively, while M08 pulls up the potential at the PD node by connecting to a VDD signal.
A circuit comprising TFTs M06 and M17 realizes a reset function. When a RESET signal outputs a high potential, the M17 discharges the PU node, and the M06 assists to charge the PD node and then turns on the M03, and further the potential at the outputting node OUTPUT is pulled down.
FIG. 2 is an operational timing diagram of the shift register unit shown in FIG. 1, and its detailed operation is as follows. The VDD is always at the high potential. In a t1 phase, the inputting terminal INPUT is at the high potential, a first clock signal CLK is at the low potential, and at this time the high potential at the inputting terminal INPUT turns on the M01, and the PU node is at the high potential at this time and alternatively charges the C1, and the M02 is turned on. Meanwhile, the INPUT signal pulls down the potential at the PD node through the M05, and the M03 is in a turn-off state at this time.
In a t2 phase, the INPUT becomes to the low potential, the first clock signal CLK is at the high potential, the capacitor C1 which is charged during the t1 phase cause a voltage at the pulling-up node PU to rise up further under a function of a bootstrap effect of the C1, the M02 remains to be in the turn-on state, and the CLK signal is transferred to the outputting terminal OUTPUT through the M02. During the t2 phase, the PU node is at the high potential all the time, the M13 is turned on, the PD is at the low potential, the M03 and M15 are turned off, and the outputting terminal OUTPUT outputs the high potential signal.
In a t3 phase, the RESET is at the high potential; at this time, the RESET turns on the M17 so as to discharge the PU node. At the same time, the M06 is also turned on, the VDD transfers the high potential to the PD node so as to cause the M15 and M03 to be turned on, so that the PU node and the outputting node OUTPUT are discharged simultaneously. During this phase, the outputting terminal OUTPUT outputs the low potential signal.
During a period of frame thereafter, the PD is in the high potential state all the time, so that the M15, M03 and M08 are in the turn-on state all the time while other transistors are in the turn-off state. In a case that a liquid crystal panel is in operation for a long time, the lifespan of these three transistors would become a critical factor for a lifespan of the entire gate driving apparatus, since the operation time of these three transistors are far longer than those of other transistors.